//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
//            (C) COPYRIGHT 2008-2012 ARM Limited.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//------------------------------------------------------------------------------
// Version and Release Control Information:
//
// File Revision       : 129471
// File Date           :  2012-05-03 18:01:17 +0100 (Thu, 03 May 2012)
// Release Information : PL401-r0p1-00eac0
//------------------------------------------------------------------------------
// Purpose             : This block takes incoming address and determines the
//                       destination for the transaction according to remap
//                       bits.
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
// Module Declaration
//------------------------------------------------------------------------------

module nic400_asib_vgalcd_mst_axi4_decode_ysyx_rv32
  (
    addr_s,
    security0,
    security3,
    security2,
    aprot,
    acache_in,
    acache_out,
    avalid_int,
    aregion_out
  );


  // ---------------------------------------------------------------------------
  //  Port definitions
  // ---------------------------------------------------------------------------

  input  [31:0]    addr_s;          // address field
  input            security0;
  input            security3;
  input            security2;
  input            aprot;
  input  [3:0]     acache_in;
  output [3:0]     acache_out;
  output [3:0]     avalid_int;
  output [3:0]     aregion_out;


  //------------------------------------------------------------------------
  // Wires
  //------------------------------------------------------------------------



  wire [2:0]       avalid_dec;
  wire [3:0]       decode_int;
  wire [3:0]       remap_decode;
  wire [3:0]       region_int;

  //------------------------------------------------------------------------
  // Registered values
  //------------------------------------------------------------------------


  // ---------------------------------------------------------------------------
  // Start of code
  // ---------------------------------------------------------------------------



  // ---------------------------------------------------------------------------
  // address decode

  assign decode_int[0] = (32'h40000000 <= addr_s) && (addr_s <= 32'h7FFFFFFF);

  assign decode_int[1] = (32'h80000000 <= addr_s) && (addr_s <= 32'h9FFFFFFF);

  assign decode_int[2] = (32'hA0000000 <= addr_s) && (addr_s <= 32'hBFFFFFFF);

  assign decode_int[3] = (32'hC0000000 <= addr_s) && (addr_s <= 32'hFFFFFFFF);



  // ---------------------------------------------------------------------------
  // remap decode

  assign remap_decode[0] = ~(aprot & security0) & decode_int[0];

  assign remap_decode[1] = ~(aprot & security0) & decode_int[3];

  assign remap_decode[2] = ~(aprot & security3) & decode_int[1];

  assign remap_decode[3] = ~(aprot & security2) & decode_int[2];


  // ---------------------------------------------------------------------------
  // valid vect decode

  assign avalid_dec[0] = ((
remap_decode[2]));
  assign avalid_dec[1] = ((
remap_decode[3]));
  assign avalid_dec[2] = ((
remap_decode[0] || remap_decode[1]));
  assign avalid_int[3] = (~|avalid_int[2:0]);

  assign avalid_int[2:0] = avalid_dec;

  // ---------------------------------------------------------------------------
  // region decode

  assign region_int[0] = 1'b0;

  assign region_int[1] = 1'b0;

  assign region_int[2] = 1'b0;

  assign region_int[3] = 1'b0;


  // ---------------------------------------------------------------------------
  // ACACHE mapping

  assign acache_out = acache_in;

  // ---------------------------------------------------------------------------
  // AREGION mapping

  assign aregion_out = region_int;


  //------------------------------------------------------------------------
  // OVL_ASSERT:
  //------------------------------------------------------------------------
// synopsys translate_off


// synopsys translate_on


endmodule

